1. Field of the Invention
This invention relates to computer system power management and, more particularly, to controlled entry and exit of low power states.
2. Description of the Related Art
As computer systems have become more powerful, power management has become a more critical part of the overall system design. This may be especially true for systems that have portable applications. To reduce the power consumed by a computer system, many computer systems employ processors that are capable of entering a standby or low power mode when there is no demand on the processor for a specified duration. In addition, to further decrease the power consumed by a system, the same low power modes may be implemented for the chipsets that are associated with the processor.
There are many ways to place a system component into a low power mode. For integrated circuits using complementary metal oxide semiconductor (CMOS) technology, the time during a transition from a logic one to a logic zero and from a logic zero to a logic one typically consumes the most power since the most current is flowing in a particular circuit. Thus, one method of decreasing system power is to reduce or halt unnecessary switching.
One power management technique involves entering a low power state by lowering the internal clock frequency when the processor is idle. When the processor is no longer idle it returns the internal clock frequency back to full frequency. However, return to full frequency should be accomplished relatively quickly so that the overall cost in time of entering the low power state does not outweigh the benefit of low power states. Therefore, it is desired to lower the clock frequency in such a way that the PLL VCO (voltage controlled oscillator) frequency is maintained (i.e. the PLL should not lose frequency lock). Maintaining the VCO frequency allows the PLL to recover from low power states faster than if it had lost frequency lock.
Since the VCO frequency is maintained while in a low power state, the internal clock frequency may by reduced by dividing the VCO clock. One method for accomplishing this is by clocking a counter with the VCO. The least significant bit (LSB) of the counter is VCO/2, which may, for example, be used as the full frequency of the internal clock. The next LSB of the counter then produces a VCO/4 clock. Selecting other bits of the counter reduces the frequency the device runs at by a factor of 4, 8, 16, 32, etc.
While the technique described above allows for rapid selection of the full frequency, it is not without its drawbacks. The power consumed by the device is proportional to the frequency. A reasonably accurate estimation of power consumption for CMOS technologies may be expressed as Power=Capacitance*Volt2*frequency. However, as described above, the method employed to reduce the frequency while maintaining frequency lock involves reducing the internal frequency by powers of 2. Consequently, ramping down the clock from full frequency to half the full frequency implies a 50% drop in power instantaneously. This sudden drop may cause the voltage on the device to jump before the voltage regulator can adjust to the reduced current demand. The situation is similar when ramping the clock back to full frequency. There is suddenly a demand for more current because the frequency has suddenly doubled. In this case, the voltage on the part may drop below the intended voltage and perhaps out of specification.
In addition to the power management techniques described above, other scenarios exist in which a sudden increase in frequency is required. For example, upon reset an internal clock may be maintained at a relatively low frequency until a local PLL achieves a lock. Subsequent to the PLL attaining lock, a rapid increase in operating frequency may be required. A similar situation may exist upon startup as well.
The unintended overshoot or undershoot of the voltage described above is potentially destructive to state stored in storage elements on the chip or may reduce the life of the chip. What is desired is a method for increasing or decreasing the frequency in an efficient manner.